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? semiconductor components industries, llc, 2013 june, 2013 ? rev. 0 1 publication order number: ncp1249a/d ncp1249a, ncp1249b high-voltage current-mode pwm controller featuring peak power excursion and extremely low stand-by power consumption the ncp1249 is a highly integrated high ? voltage pwm controller capable of delivering a rugged and high performance offline power supply with extremely low no ? load consumption. with a supply range up to 30 v, the controller hosts a jittered 65 ? khz switching circuitry operated in peak current mode control. when the power on the secondary side starts to decrease, the controller automatically folds back its switching frequency down to a minimum level of 26 khz. as the power further goes down, the part enters skip cycle while freezing the peak current setpoint. to help build rugged converters, the controller features several key protective features: a internal brown ? out, a non ? dissipative over power protection for a constant maximum output current regardless of the input voltage and two latched over voltage protection inputs ? either through a dedicated pin or via the vcc input. the controller architecture is arranged to authorize a transient peak power excursion when the peak current hits the limit. at this point, the switching frequency is increased from 65 khz to 130 khz until the peak requirement disappears. the timer duration is then modulated as the converter crosses a peak power excursion mode (long) or undergoes a short circuit (short). features ? high ? voltage current source for lossless start ? up sequence ? remote input for standby operation control ? automatic and lossless x2 capacitors discharge function ? 65 ? khz fixed ? frequency current ? mode control operation with 130 ? khz excursion ? internal and adjustable over power protection (opp) circuit ? internal brown ? out protection circuit ? frequency foldback down to 26 khz and skip ? cycle in light load conditions ? adjustable ramp compensation ? internally fixed 4 ? ms soft ? start ? 100% to 25% timer reduction from overload to short ? circuit fault ? frequency jittering in normal and frequency foldback modes ? latched ovp input for improved robustness and latched ovp on v cc ? up to 30 v v cc maximum rating ? +300 ma/ ? 500 ma source/sink drive capability ? extremely low no ? load standby power ? option for auto ? recovery or latched short ? circuit protection ? internal thermal shutdown with hysteresis ? these are pb ? free devices typical applications ? converters requiring peak ? power capability such as printers power supplies, ac ? dc adapters for game stations pin connections (top view) soic ? 9 nb d suffix case 751bp http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information 1 9 ncp1249x65 = specific device code x = a or b a = assembly location l = wafer lot y = year w = work week = pb ? free package marking diagram ncp1249x65 alyw 1 9 gnd drv vcc hv rem fb cs opp/latch x2 1
ncp1249a, ncp1249b http://onsemi.com 2 figure 1. typical application example table 1. pin functions pin no pin name function pin description 1 x2 x2 ? capacitors discharge when the voltage on this pin disappears, the controller ensures the x2 ? capacitors discharge. 2 rem remote input initiates ultra low consumption mode (off ? mode) when brought above 8 v. 3 fb feedback pin connecting an opto ? coupler to this pin allows regulation. 4 cs current sense + ramp compensation this pin monitors the primary peak current but also offers a means to introduce slope compensation. 5 opp/latch adjust the over power protection latches off the part a resistive divider from the auxiliary winding to this pin sets the opp compensation level. when brought above 3 v, the part is fully latched off. 6 gnd ? the controller ground. 7 drv driver output the driver?s output to an external mosfet gate. 8 vcc supplies the controller this pin is connected to an external auxiliary voltage and supplies the controller. when above a certain level, the part fully latches off. 9 nc ? increases insulation distance between high and low voltage pins. 10 hv high ? voltage input this pin provides a charging current during start ? up and auto ? recovery faults but also a means to efficiently discharge the input x2 capacitors. table 2. options and ordering information device overload protection switching frequency peak frequency package shipping ? NCP1249AD65R2G latched 65 khz 130 khz soic ? 9 (pb ? free) 2500 / tape & reel ncp1249bd65r2g autorecovery 65 khz 130 khz soic ? 9 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging. specifications brochure, brd8011/d.
ncp1249a, ncp1249b http://onsemi.com 3 figure 2. internal circuit architecture q q 65 khz vdd modulation vcc drv vcc management, rramp leb vdd rfb ipflag 4ms ss gnd cs fb 600 ns time constant opp/ latch foldback vskip vlatch the soft ? start is activated during : ? the startup sequence + vlimit vfold s r q q clamp 20 constant vovp 1 s blanking 4 hiccup ovp gone ? uvlo hv x2 rem tsd hv startup por frequency ipflag logic and fault timer x2 timer remote timer 300 mv peak current freeze vdd /pwm_ on brown ? out r s r q q bo _ok frequency clock bo _bias en ? the auto ? recovery burst mode vopp vlimit + vopp rst resets if vcc < 3 v s time s r up counter idischarge vhv rem timer x2 & vcc discharge
ncp1249a, ncp1249b http://onsemi.com 4 table 3. maximum ratings table symbol rating value unit v cc power supply voltage, vcc pin, continuous voltage ? 0.3 to 30 v v hv high voltage (hv) pin (pin 10) ?0.3 to 500 v vpin_x maximum voltage on low power pins (x2, rem, fb, cs, opp) ? 0.3 to 10 v v drv maximum voltage on drive pin ? 0.3 to v cc +0.3 v i opp maximum injected current into the opp pin ? 2 ma r j ? a thermal resistance junction ? to ? air 211 c/w t j,max maximum junction temperature 150 c storage temperature range ? 60 to +150 c esd capability, hbm model (all pins except hv) per jedec standard jesd22, method a114e 2 kv esd capability, machine model per jedec standard jesd22, method a115a 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78. table 4. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol rating pin min typ max unit hv startup current source v hv_min minimum voltage for current source operation (v cc = 4v) 10 ? 30 60 v i start1 current flowing out of vcc pin (v cc = 0 v) 8, 10 0.2 0.7 1 ma i start2 current flowing out of vcc pin (v cc = v cc_on ? 0.5 v) 8, 10 6 10 15 ma v cc_inhibit v cc level for i start1 to i start2 transition 8 0.5 1 1.25 v i start_off off ? state leakage current (v hv = 500 v, v cc = 15 v) 10 ? 15 ? a i hv_off mode_1 hv pin leakage current when off ? mode is active (v hv = 141 v) 10 ? ? 15 a i hv_off mode_2 hv pin leakage current when off ? mode is active (v hv = 325 v) 10 ? ? 19 a v hv_min_off ? mode minimum voltage on hv pin during off ? mode (v _rem = 10v, v cc = 0v) 10 ? ? 10 v supply section v cc_on v cc increasing level at which driving pulses are authorized 8 16 18 20 v v cc_off v cc decreasing level at which driving pulses are stopped 8 9.5 10 11 v v cc_hyst hysteresis v cc_on ? v cc_off 8 6 ? ? v v cc_bias v cc level during a fault 8 4.7 5.5 6.5 v i cc1 internal ic consumption with i fb =75 a, f sw =65 khz and c l = 0 8 ? 1.6 2.6 ma i cc2 internal ic consumption with i fb =75 a, f sw =65 khz and c l = 1 nf 8 ? 2.3 3.4 ma i cc3 internal ic consumption with i fb =75 a, f sw =130 khz and c l = 0 8 ? 1.9 2.9 ma i cc4 internal ic consumption with i fb =75 a, f sw =130 khz and c l = 1 nf 8 ? 3.3 4.4 ma i cc_skip internal ic consumption while in skip mode 8 660 960 1360 a i cc_latch internal ic consumption during latch off mode 8 ? 350 520 a brown ? out v _bo_on brown ? out turn ? on threshold (v hv going up) 10 92 101 110 v v _bo_off brown ? out turn ? off threshold (v hv going down) 10 84 93 102 v bo_timer timer duration for line cycle drop ? out 10 40 ? 100 ms 2. guaranteed by design 3. see characterization table for linearity over negative bias voltage ? we recommend keeping the level on pin 5 below ? 300 mv. 4. a 1 ? m resistor is connected from pin 4 to the ground for the measurement.
ncp1249a, ncp1249b http://onsemi.com 5 table 4. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating x2 discharge circuitry v th_x2 x2 timer disable switch threshold voltage 1 1 1.5 2 v v th_x2_hyst hysteresis on the x2 pin 1 ? 100 ? mv v _x2_clamp x2 input clamp voltage 1 ? 4 ? v x2_timer x2 timer duration 1 70 ? 140 ms i _x2_leak x2 input leakage current (v _x2 = 2.5 v) 1 ? ? 0.3 a i _x2_dis maximum discharge switch current (v cc = 10v) 10 6 10 13 ma drive output t r output voltage rise ? time @ c l = 1 nf, 10 ? 90% of output signal 7 ? 40 80 ns t f output voltage fall ? time @ c l = 1 nf, 10 ? 90% of output signal 7 ? 30 70 ns r oh source resistance 7 ? 13 ? r ol sink resistance 7 ? 6 ? i source peak source current, v gs = 0 v ? note 1 7 300 ma i sink peak sink current, v gs = 12 v ? note 1 7 500 ma v drv_low drv pin level at v cc close to v cc_off with a 33 ? k resistor to gnd 7 8 ? ? v v drv_high drv pin level at v cc = v ovp ? 0.2 v, drv unloaded 7 10 12 14 v current comparator i ib input bias current @ 0.8 v input level on pin 4 4 0.02 a v limit maximum internal current setpoint ? tj = 25 c ? pin 5 grounded 4 0.744 0.8 0.856 v v limit maximum internal current setpoint ? tj from ? 40 to 125 c ? pin 5 grounded 4 0.72 0.8 0.88 v v fold_cs default internal voltage set point for frequency foldback trip point 47% of v limit 4 475 mv v freeze_cs internal peak current setpoint freeze ( 31% of v limit ) 4 250 mv t del propagation delay from current detection to gate off ? state 4 100 150 ns t leb leading edge blanking duration 4 300 ns t ss internal soft ? start duration activated upon startup, auto ? recovery ? 4 ms i oppo setpoint decrease for pin 5 biased to ?250 mv ? (note 2) 4 31.3 % i oopv voltage setpoint for pin 5 biased to ? 250 mv ? (note 2) tj from ? 40 to 125 c 4 0.5 0.55 0.62 v i opps setpoint decrease for pin 5 grounded 4 0 % internal oscillator f osc_nom oscillation frequency, v fb < v fbtrans , pin 5 grounded ? 57 65 71 khz v fbtrans feedback voltage above which f sw increases 3 3.2 v f osc_max maximum oscillation frequency for v fb above v fbmax ? 115 130 140 khz v fbmax feedback voltage above which f sw is constant 3 3.8 4 4.2 v d max maximum duty ratio ? 76 80 84 % f jitter frequency jittering in percentage of f osc ? 5 % f swing swing frequency over the whole frequency range ? 240 hz 2. guaranteed by design 3. see characterization table for linearity over negative bias voltage ? we recommend keeping the level on pin 5 below ? 300 mv. 4. a 1 ? m resistor is connected from pin 4 to the ground for the measurement.
ncp1249a, ncp1249b http://onsemi.com 6 table 4. electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 12 v unless otherwise noted) symbol unit max typ min pin rating remote section v _rem_on remote pin voltage below which is the off ? mode deactivated (v rem going down) (v cc = 0 v) 2 1 1.5 2 v v _rem_off remote pin voltage above which is the off ? mode activated (v rem going up) 2 7.2 8 8.8 v rem_timer remote timer duration 2 70 ? 140 ms r _sw_rem internal remote pull down switch resistance 2 1000 ? 3000 i _rem_leak remote input leakage current (v rem = 9 v) (note 1) 2 ? 0.02 1 a feedback section r up(fb) internal pull ? up resistor 3 17 k r eq equivalent ac resistor from fb to gnd 3 10 15 20 k i ratio pin 3 to current setpoint division ratio 3,4 4 ? v freeze_fb feedback voltage below which the peak current is frozen 3 1 v frequency foldback v fold_fb frequency foldback level on the feedback pin ? 47% of maximum peak current 3 1.9 v f trans transition frequency below which skip ? cycle occurs ? 22 26 30 khz v fold_end end of frequency foldback feedback level, f sw = f min 3 1.5 v v skip skip ? cycle level voltage on the feedback pin 3 400 mv skip hysteresis hysteresis on the skip comparator ? note 1 3 30 mv internal slope compensation v ramp internal ramp level @ 25 c ? note 3 4 2.5 v r ramp internal ramp resistance to cs pin 4 20 k protections v latch latching level input 5 2.7 3 3.3 v t latch ? blank blanking time after drive turn off 5 1 s t latch ? count number of clock cycles before latch confirmation ? 4 ? t latch ? del ovp detection time constant 5 600 ns v ovl feedback voltage at which an overload is considered ? opp pin is grounded 3 3.2 v v sc feedback voltage above which a short ? circuit is considered 3 3.9 4.1 4.3 v timer 1 fault timer duration when 3.2 < v fb < 4.1 v ? overload ? 100 200 300 ms timer 2 fault timer duration when v fb > 4.1 v is timer 1 /4 ? short ? circuit condition ? 25 50 75 ms v ovp latched over voltage protection on the v cc rail 8 26 27.5 29 v t ovp_del delay before ovp on v cc confirmation 8 20 30 s t a ? rec_timer auto ? recovery timer duration ? 0.7 ? ? s temperature shutdown t tsd temperature shutdown t j going up ? 150 c t tsd(hys) temperature shutdown hysteresis ? 30 c 2. guaranteed by design 3. see characterization table for linearity over negative bias voltage ? we recommend keeping the level on pin 5 below ? 300 mv. 4. a 1 ? m resistor is connected from pin 4 to the ground for the measurement.
ncp1249a, ncp1249b http://onsemi.com 7 typical characteristics figure 3. minimum current source operation, v hv_min figure 4. high voltage startup current flowing out of v cc pin, i start1 temperature ( c) temperature ( c) 110 80 35 20 5 ? 10 ? 25 ? 40 17 18 19 20 21 22 23 24 0.5 0.6 0.7 0.8 0.9 figure 5. high voltage startup current flowing out of vcc pin, i start2 figure 6. off ? state leakage current, i start_off temperature ( c) temperature ( c) figure 7. hv pin current during off ? mode, i hv_off_mode_1 figure 8. hv pin current during off ? mode, i hv_off_mode_2 temperature ( c) temperature ( c) v hv_min (v) i start1 (ma) i start2 (ma) i start_off ( a) i hv_off ? mode_1 ( a) i hv_off ? mode_2 ( a) 50 65 95 125 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 9 10 11 12 13 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 10 11 12 13 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 110 80 35 20 5 ? 10 ? 25 ? 40 7.0 7.5 8.0 8.5 9.0 9.5 10.0 50 65 95 125 9 10 11 12 13 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125
ncp1249a, ncp1249b http://onsemi.com 8 typical characteristics figure 9. v cc increasing level at which driving pulses are authorized, v cc_on figure 10. v cc decreasing level at which driving pulses are stopped, v cc_off temperature ( c) temperature ( c) 17.0 17.2 17.4 17.6 17.8 18.0 9.8 9.9 10.0 10.1 10.2 figure 11. v cc hysteresis, v cc_hyst figure 12. v cc level at fault modes, v cc_bias temperature ( c) temperature ( c) figure 13. v cc level for i start1 to i start2 transition, v cc_inhibit temperature ( c) 0.7 0.8 0.9 1.0 1.1 v cc_on (v) v cc_off (v) v cc_hyst (v) v cc_bias (v) v cc_inhibit (v) 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 7.5 7.6 7.7 7.8 7.9 8.0 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 5.0 5.2 5.4 5.6 5.8 6.0 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 14. internal ic consumption during latch ? off mode, i cc_latch temperature ( c) i cc_latch ( a) 250 300 350 400 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125
ncp1249a, ncp1249b http://onsemi.com 9 typical characteristics figure 15. brown ? out turn ? on threshold, v _bo_on temperature ( c) figure 16. brown ? out turn ? off threshold, v _bo_off figure 17. x2 timer disable switch threshold, v th_x2 temperature ( c) temperature ( c) v _bo_on (v) v _bo_off (v) v th2_x2 (v) 102.0 102.5 103.0 103.5 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 89.0 89.5 90.0 90.5 91.0 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 110 80 35 20 5 ? 10 ? 25 ? 40 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.8 50 65 95 125 1.7 figure 18. x2 input clamp voltage, v _x2_clamp temperature ( c) 3.4 3.5 3.6 3.7 3.8 3.9 4.1 4.2 v _x2_clamp (v) 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 4.0 figure 19. maximum x2 cap discharge current, i _x2_dis temperature ( c) 8.0 8.5 9.0 10.0 10.5 11.0 i x2_dis (ma) 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 9.5 figure 20. off ? mode turn ? off threshold, v _rem_on temperature ( c) 1.4 1.5 1.6 1.7 1.8 v _rem_on (v) 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125
ncp1249a, ncp1249b http://onsemi.com 10 typical characteristics figure 21. off ? mode turn ? on threshold, v _rem_off temperature ( c) figure 22. internal remote pull down switch resistance, r _sw_rem temperature ( c) 1900 2000 2100 2200 2300 2400 v _rem_off (v) r _sw_rem ( ) 1.4 1.5 1.6 1.7 1.8 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 23. output voltage rise ? time, t r figure 24. output voltage fall ? time, t f temperature ( c) temperature ( c) t r (ns) t f (ns) 35 40 45 50 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 20 25 30 35 40 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 25. source resistance, r ol figure 26. sink resistance, r oh temperature ( c) temperature ( c) r ol ( ) r oh ( ) 5 6 7 8 9 10 11 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 11 12 13 15 16 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 14
ncp1249a, ncp1249b http://onsemi.com 11 typical characteristics figure 27. drv pin level at v cc close to v cc_off , v drvlow figure 28. drv pin level at v cc close to v ovp , v drvhigh temperature ( c) temperature ( c) 11.0 11.5 12.0 12.5 13.0 13.5 14.0 v drv_low (v) v drv_high (v) 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 9.0 9.5 10.0 10.5 11.0 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 29. maximum internal current set ? point, v limit figure 30. default internal voltage set point for frequency foldback, v fold_cs temperature ( c) temperature ( c) 0.75 0.77 0.79 0.81 0.83 0.85 v limit (v) v fold_cs (mv) 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 470 480 490 500 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 31. internal peak current set ? point freeze, v freeze_cs figure 32. propagation delay from current detection to gate off ? state, t del temperature ( c) temperature ( c) 230 235 240 245 250 v freeze_cs (mv) t del (ns) 49 50 51 52 53 54 55 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125
ncp1249a, ncp1249b http://onsemi.com 12 typical characteristics figure 33. leading edge blanking duration, t leb figure 34. internal soft ? start duration, t ss temperature ( c) temperature ( c) t leb (ns) t ss (ms) 290 300 310 320 330 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 3.9 4.0 4.1 4.2 4.3 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 35. cs voltage setpoint for opp, i oppv figure 36. set ? point decrease for opp, i oppo temperature ( c) temperature ( c) 0.50 0.52 0.54 0.56 0.58 0.60 i oppv i oppo (%) 28.0 28.5 29.0 29.5 30.0 30.5 31.0 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 37. oscillation frequency, f osc_nom figure 38. maximum oscilation frequency, f osc_max temperature ( c) temperature ( c) 120 125 130 135 140 f osc_nom (hz) f osc_max (hz) 61 63 65 67 69 71 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125
ncp1249a, ncp1249b http://onsemi.com 13 typical characteristics figure 39. maximum duty ? cycle, d max figure 40. swing frequency, f swing temperature ( c) temperature ( c) d max (%) f swing (hz) 79.0 79.2 79.4 79.6 79.8 80.0 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 210 215 220 225 230 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 41. equivalent ac resistor from fb to gnd, r eq figure 42. fb to current set ? point division ratio, i ratio temperature ( c) temperature ( c) 3.90 3.95 4.00 4.05 4.10 r eq (k ) i ratio ( ? ) 11 12 13 14 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 43. frequency foldback level, v fold_fb figure 44. transition frequency below which skip ? cycle occurs, f trans temperature ( c) temperature ( c) 1.80 1.85 1.90 1.95 2.00 25.0 25.5 26.0 26.5 v fold_fb (v) f trans (hz) 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125
ncp1249a, ncp1249b http://onsemi.com 14 typical characteristics figure 45. skip ? cycle level voltage on the feedback pin, v skip figure 46. latching level input, v latch temperature ( c) temperature ( c) 400 402 404 406 408 410 v skip (mv) v latch (v) 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 3.00 3.02 3.04 3.06 3.08 3.10 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 47. over voltage protection on v cc rail, v ovp figure 48. ovp detection time constant, t ovp_del temperature ( c) temperature ( c) v ovp (v) t ovp_del ( s) 26.5 26.7 26.9 27.1 27.3 27.5 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 18.0 18.5 19.0 19.5 20.0 20.5 21.0 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 49. fault timer duration ? overload, timer1 figure 50. fault timer duration ? short ? circuit condition, timer2 temperature ( c) temperature ( c) timer1 (ms) timer2 (ms) 202 203 204 205 206 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 50.0 50.5 51.0 51.5 52.0 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125
ncp1249a, ncp1249b http://onsemi.com 15 typical characteristics figure 51. internal ic consumption, i cc1 temperature ( c) i cc1 (ma) 1.5 1.6 1.7 1.8 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 52. internal ic consumption, i cc2 temperature ( c) 2.30 2.35 2.40 2.45 2.50 i cc2 (ma) 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 temperature ( c) i cc4 (ma) 3.1 3.2 3.3 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 53. internal ic consumption, i cc3 temperature ( c) 1.5 1.6 1.7 1.8 i cc3 (ma) 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125 figure 54. internal ic consumption, i cc4 figure 55. internal ic consumption during skip mode, i cc_skip temperature ( c) 0.5 0.6 0.7 0.8 0.9 i cc_skip (ma) 110 80 35 20 5 ? 10 ? 25 ? 40 50 65 95 125
ncp1249a, ncp1249b http://onsemi.com 16 application information introduction the ncp1249 implements a standard current mode architecture where the switch ? off event is dictated by the peak current setpoint. this component represents the ideal candidate where low part ? count and cost effectiveness are the key parameters, particularly in low ? cost ac ? dc adapters, open ? frame power supplies etc. the ncp1249 brings all the necessary components normally needed in today modern power supply designs, bringing several enhancements such as a non ? dissipative opp, a brown ? out protection or peak power excursion for loads exhibiting variations over time. accounting for the new needs of extremely low standby power requirements, the part includes an automatic x2 ? capacitor discharge circuitry that prevents the designer from installing power ? consuming resistors across the front ? end filtering capacitors. the controller is also able to enter a deep sleep mode via its dedicated remote pin. ? high ? voltage start ? up: low standby power results cannot be obtained with the classical resistive start ? up network. in this part, a high ? voltage current ? source provides the necessary current at start ? up and turns off afterwards. ? internal brown ? out pr otection: a portion of the bulk voltage is internally sensed via the high ? voltage pin monitoring (pin 10). when the voltage on this pin is too low, the part stops pulsing. no re ? start attempt is made until the controller senses that the voltage is back within its normal range. when the brown ? out comparator senses the voltage is acceptable, it sends a general reset to the controller (de ? latch occurs) and authorizes to re ? start. ? x2 ? capacitors discharge capability: per iec ? 950 standard, the time constant of the front ? end filter capacitors and their associated discharge resistors must be less than 1 s. this is to avoid electrical stress when the user unplugs the converter and inadvertently touches the power cord terminals. by providing an automatic means to discharge the x2 capacitors, the ncp1249 prevents the designer from installing the discharge resistors, helping to further save power. ? off ? mode: off ? mode helps to achieve low power consumption of an smps during no load conditions. the ic goes into off ? mode when the rem pin is brought higher than the internal reference voltage v _rem_off . the disable input is pulled low, vcc capacitor is discharged and consumption of all internal blocks is reduced once the off ? mode is activated. off mode is terminated when remote pin voltage crosses v _rem_on threshold or application is unplugged from the mains. ? current ? mode operation with internal slope compensation: implementing peak current mode control at a fixed 65 ? khz frequency, the ncp1249 offers an internal ramp compensation signal that can easily by summed up to the sensed current. sub harmonic oscillations can thus be compensated via the inclusion of a simple resistor in series with the current ? sense information. ? frequency excursion: when the power demand forces the peak current setpoint to reach the internal limit (0.8 v/r sense typically), the frequency is authorized to increase to let the converter deliver more power. the frequency excursion stops when 130 khz are reached. ? internal opp: by routing a portion of the negative voltage present during the on ? time on the auxiliary winding to the dedicated opp pin (pin 5), the user has a simple and non ? dissipative means to alter the maximum peak current setpoint as the bulk voltage increases. if the pin is grounded, no opp compensation occurs. if the pin receives a negative voltage down to ?250 mv, then a peak current reduction down to 31.3% typical can be achieved. for an improved performance, the maximum voltage excursion on the sense resistor is limited to 0.8 v. ? emi jittering: an internal low ? frequency modulation signal varies the pace at which the oscillator frequency is modulated. this helps spreading out energy in conducted noise analysis. to improve the emi signature at low power levels, the jittering will not be disabled in frequency foldback mode (light load conditions). ? frequency foldback capability: a continuous flow of pulses is not compatible with no ? load/light ? load standby power requirements. to excel in this domain, the controller observes the feedback pin and when it reaches a level of 1.5 v, the oscillator then starts to reduce its switching frequency as the feedback level continues to decrease. when the feedback pin reaches 1 v, the peak current setpoint is internally frozen and the frequency continues to decrease. it can go down to 26 khz (typical) reached for a feedback level of 450 mv roughly. at this point, if the power continues to drop to 400 mv, the controller enters classical skip ? cycle mode. ? internal soft ? start: a soft ? start precludes the main power switch from being stressed upon start ? up. in this controller, the soft ? start is internally fixed to 4 ms. soft ? start is activated when a new startup sequence occurs or during an auto ? recovery hiccup. ? latch input: the ncp1249 includes a latch input (pin 5) that can be used to sense an overvoltage condition on the adapter. if this pin is brought higher than the internal reference voltage v latch , then the circuit permanently latches off. the vcc pin is pulled down to a fixed level, keeping the controller latched. the latch reset occurs when the user disconnects the adapter from the mains.
ncp1249a, ncp1249b http://onsemi.com 17 ? v cc ovp: a latched ovp protects the circuit against v cc runaways. the fault must be present at least 20 s to be validated. reset occurs when the user disconnects the adapter from the mains. ? short ? circuit protection: short ? circuit and especially over ? load protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the aux winding level does not properly collapse in presence of an output short). here, every time the internal 0.8 ? v maximum peak current limit is activated (or less when opp is used), an error flag is asserted and a time period starts, thanks to the programmable timer. the controller can distinguish between two faulty situations: ? there is an extra demand of power, still within the power supply capabilities. in that case, the feedback level is in the vicinity of 3.2 ? 4 v. it corresponds to 0.8 v as the maximum peak current setpoint without opp. the timer duration is then 100% of its normal value. if the fault disappears, e.g. the peak current setpoint no longer hits the maximum value (e.g. 0.8 v at no opp), then the timer is reset. ? the output is frankly shorted. the feedback level is thus pushed to its upper stop (4.5 v) and the timer is reduced to 25% of its normal value. ? in either mode, when the fault is validated, all pulses are stopped and the controller enters an auto ? recovery burst mode, with a soft ? start sequence at the beginning of each cycle. please note the presence of a divider by two which ignores one hiccup cycle over two (double hiccup type of burst). ? as soon as the fault disappears, the smps resumes operation. please note that some version offers an auto ? recovery mode as we just described, some do not and latch off in case of a short circuit. start ? up sequence the start ? up sequence of the ncp1249 involves a high ? voltage current source whose input is in pin 10. as this start ? up source also performs line sensing for brown ? out operation, it is recommended to wire it according to figure 56 sketch. . 1 2 3 4 8 6 7 5 10 9 l1 l2 ic vbulk vcc to x2 discharge figure 56. the startup resistor can be connected to the input mains for further power dissipation reduction in this drawing, the high ? voltage pin is not connected to the bulk, but to the full ? wave rectified ac input. it is important to keep this configuration as the x2 circuitry will also use it. the first step starts with the calculation of the needed v cc capacitor which will supply the controller until the auxiliary winding takes over. experience shows that this time t 1 can be between 5 and 20 ms. considering that we need at least an energy reservoir for a t 1 time of 10 ms, the v cc capacitor must be larger than: c vcc i cc4 t 1 v cc _ on v cc _ off 3m 10 m 18 10 3.75 f (eq. 1) in this calculation, we adopted the consumption at the highest switching frequency since this is the point at which the ic will work in cold ? start case. let us select a 4.7 f capacitor at first and experiments in the laboratory will let us know if we were too optimistic for t 1 . the v cc capacitor being known, we can now evaluate the charging time to bring the v cc voltage from 0 to the v cc_on of the ic, 18 v typical. this time sequence can actually be split into two events: 0 v to v cc_inhibit and v cc_inhibit to v cc_on . this is because the hv source is protected from short ? circuits on the vcc pin. in case this happens, the source detects that the v cc voltage is less than v cc_inhibit and only delivers i start1 which is below 1 ma: the die power consumption is maintained to the lowest value. in normal operation, when the voltage has normally reached v cc_inhibit , the source toggles to the full current and charges the v cc capacitor at a larger current, i start2 . the first time duration involves i start1 and v cc_inhibit.
ncp1249a, ncp1249b http://onsemi.com 18 t start1 v cc_inhibit c vcc i start1 1 4.7 700 6.7 ms (eq. 2) the second duration involves v cc_on and i start2 : t start2 v cc_on v cc_inhibit c vcc i start2 (18 1) 4.7 10 m 8ms (eq. 3) the total start ? up time is thus around 14 ? 15 ms. figure 57. the v cc at start ? up is made of two segments given the short ? circuit protection implemented on the hv source in case the v cc capacitor must be increased to cope with no ? load standby requirements, there is plenty of margin to keep the total start ? up sequence duration below 1 s. assume the v cc capacitor is 100 f, then the total start ? up time would be below 400 ms. brown ? out circuitry the ncp1249 features, on its hv pin, a true ac line monitoring circuitry ? refer to figure 58. this system includes a minimum start ? up threshold and auto ? recovery brown ? out protection; both of them independent of the input voltage ripple. the thresholds are fixed, but they are designed to fit most of the standard ac ? dc converter applications. when the hv pin voltage drops below v _bo_off threshold for more than 50 ms, the brown ? out condition is detected and confirmed. thus the controller stops operation ? refer to figure 59. the v cc capacitor is discharged to vcc_ bias level. the hv current source maintains v cc at vcc_ bias level until the input voltage is back above v _bo_on . the controller then fully discharges v cc capacitor first to restart internal logic. standard startup attempt is then placed by the controller. figure 58. simplified block diagram of brown ? out detection circuitry the internal hv bo sensing network is formed by high impedance resistor divider with minimum resistance of 20 m . this solution reducing power losses during off ? mode and thus helps to pass maximum standby power consumption limit. the internal bo network solution provides excellent noise and pcb leakage currents immunity that is hard to achieve when using external resistor divider built from smt chip resistors.
ncp1249a, ncp1249b http://onsemi.com 19 figure 59. brown ? out event detection x2 and v cc discharge circuitry the ncp1249 x2 discharge circuitry uses dedicated pin (x2) together with external charge pump sensing network to detect whether is application plugged into the mains or not. advantage of this solution is that the internal ic consumption can be reduced to extremely low level by keeping all internal blocks unbiased except simple and low consuming x2 timer disable circuitry. the internal x2 timer with typical duration of 100 ms is used to overcome unwanted activation of the x2 discharge switch in case of ac line dropout. the internal x2 discharge switch is activated once the x2 timer elapses. the hv startup current source is enabled in the same time thus the discharge path for x2 capacitor exists ? refer to figure 60. figure 60. simplified block diagram of x2 and vcc capacitor discharge circuitry the time duration of x2 capacitors discharging could be calculated by: t u c x1,2 i _x2_dis c x1,2 (eq. 4) the x2 capacitor discharging process can be interrupted by increasing voltage on x2 pin back above v th_x2 . the over temperature protection block is active during discharging process to protect controller chip against unwanted overheat that could occur in case the x2 pin is opened and the high voltage is present on the hv pin (like during open ? short pins testing for instance). the x2 discharge switch is also activated to discharge v cc capacitor when entering into fault mode (latch mode, auto ? recovery mode or the hv pin voltage drops below v _bo_off threshold for more than 50 ms), off ? mode and also before controller v cc restart.
ncp1249a, ncp1249b http://onsemi.com 20 remote input with remote timer the ncp1249a/b features dedicated input (rem pin) that allows user to activate ultra low consumption mode during which the ic consumption is reduced to only very low hv pin leakage current (refer to i hv_off ? mode_1 and i hv_off ? mode_2 parameters). the off ? mode is activated when remote pin voltage exceeds v _rem_off threshold (8 v typically). normal operating mode (i.e. on ? mode) is then initiated again when remote input voltage drops back below v _rem_on threshold (1.5 v typically) ? refer to figure 61 for better understanding. figure 61. simplified block diagram of remote control input the off ? mode is activated when the remote input is pulled up by auxiliary remote supply (refer to figure 61.). the normal operation mode is then activated when dedicated opto ? coupler pulls the remote input down. there could occur situation, in the application, that the auxiliary remote supply stays charged while the secondary bias has been lost. the application then cannot restart until the auxiliary remote supply capacitor fully discharges. thus the remote input hosts internal pull down switch and remote timer with duration rem_timer . the controller pulls down remote pin using this circuitry in order to allow correct application restart in case the auxiliary bias capacitor (c1) stays charged while the secondary side is fully discharged already. the remote timer is activated each time the application starts after these events: ? start after application was plugged into the mains (x2 discharger signal resets remote timer latch in this case) ? start after application has been un ? latched by re ? plugging to the mains (x2 discharger signal resets remote timer latch in this case) ? restart from fault conditions in auto ? recovery versions ? restart after v cc has been lost while remote pin was at low state ? restart after bo event ? restart after ovp/otp event the remote timer helps to assure correct application start or re ? start from fault conditions by forcing controller operation for 100 ms typically. however, the secondary controller drives remote pin via opto ? coupler during normal operating conditions in order to switch between on ? mode and off ? mode states. the on ? mode is activated for very short time during no ? load conditions ? just to re ? fill primary and secondary capacitors to keep application biased. the remote timer thus cannot be used in this case because it would increase no ? load power consumption by forcing application on ? mode operation for longer time than it is naturally needed. the remote timer with internal pull down switch is thus not activated in this case (i.e. when application restarts from off ? mode operation). operating status diagram the ncp1249a/b v cc management behavior is clearly described in status diagram on figure 62.
ncp1249a, ncp1249b http://onsemi.com 21 extra low consumption x2 cap discharge drv = 0 vcc ? >0v hv ? >0v remote mode vcc = floating drv = 0 v_rem> v_rem_off charge v cc vcc ? >22v drv = 0 start vcc ? >5v drv = 0 vcc_fault vcc = 5v drv = 0 t a ? rec _timer =1 vcc < vcc_on bo (v cc >v ccon )&bo operation vcc = vcc_off ? vcc_max drv = 1 bo efficient operating mode v_ rem >v_ rem_on latch vcc = 5v drv = 0 x2 discharge = 0 bo fault vcc = 5v drv = 0 x2 timer vcc = xv drv = x x2_timer = 1 remote discharge vcc ? >5v drv = 0 bo reset bo t a ? rec_timer =1 x2_timer = 0 x2 detect = 0 & x2_timer = 1 x2 detect = 0 x2 detect = 1 vcc = 5v vcc > 5v (v cc >v cc_off ) & bo & (v _ rem >v_ rem_on )& latch = 0 tsd vcc = xv drv = 0 tsd=1 vcc > 1v ??????????? ??????????? ??????????? ??????????? ??????????? ??????????? ??????????? ??????????? ??????????? ??????????? ??????????? ?? ? >0.7v drv = 0 figure 62. v cc management status diagram internal over power protection there are several known ways to implement over power protection (opp), all suffering from particular problems. these problems range from the added consumption burden on the converter or the skip ? cycle disturbance brought by the current ? sense offset. a way to reduce the power capability at high line is to capitalize on the negative voltage swing present on the auxiliary diode anode. during the turn ? on time, this point dips to ? nv in , n being the turns ratio between the primary winding and the auxiliary winding. the negative plateau observed on figure 63 will have amplitude depending on the input voltage. the idea implemented in this chip is to sum a portion of this negative swing with the 0.8 v internal reference level. for instance, if the voltage swings down to ? 150 mv during the on time, then the internal peak current set point will be fixed to 0.8 ? 0.150 = 650 mv. the adopted principle appears in figure 64 and shows how the final peak current set point is constructed. figure 63. the signal obtained on the auxiliary winding swings negative during the on ? time let?s assume we need to reduce the peak current from 2.5 a at low line, to 2 a at high line. this corresponds to a 20% reduction or a set point voltage of 640 mv. to reach this level, then the negative voltage developed on the opp pin must reach: v opp 640 m 800 m ? 160 mv (eq. 5)
ncp1249a, ncp1249b http://onsemi.com 22 figure 64. the opp circuitry affects the maximum peak current set point by summing a negative voltage to the internal voltage reference let us assume that we have the following converter characteristics: v out = 19 v v in = 85 to 265 v rms n 1 = n p :n s = 1:0.25 n 2 = n p :n aux = 1:0.18 given the turns ratio between the primary and the auxiliary windings, the on ? time voltage at high line (265 vac) on the auxiliary winding swings down to: v aux ? n 2 v in,max ? 0.18 375 ? 67.5 v (eq. 6) to obtain a level as imposed by (eq. 5), we need to install a divider featuring the following ratio: div 0.16 67.5 2.4 m (eq. 7) if we arbitrarily fix the pull ? down resistor r oppl to 1 k , then the upper resistor can be obtained by: r oppu 67.5 0.16 0.16
1k 421 k (eq. 8) if we now plot the peak current set point obtained by implementing the recommended resistor values, we obtain the following curve (figure 65): figure 65. the peak current regularly reduces down to 20% at 375 v dc v bulk 375 80% 100% peak current setpoint the opp pin is surrounded by zener diodes stacked to protect the pin against esd pulses. these diodes accept some peak current in the avalanche mode and are designed to sustain a certain amount of energy. on the other side, negative injection into these diodes (or forward bias) can cause substrate injection which can lead to an erratic circuit behavior. to avoid this problem, the pin is internal clamped slightly below ?300 mv which means that if more current is injected before reaching the esd forward drop, then the maximum peak reduction is kept to 40%. if the voltage finally forward biases the internal zener diode, then care must be taken to avoid injecting a current beyond ?2 ma. given the value of r oppu , there is no risk in the present example. finally, please note that another comparator internally fixes the maximum peak current set point to 0.8 v even if the opp pin is adversely biased above 0 v. for optimum performance over temperature, we recommend keeping the low ? side opp resistor below 3 k .
ncp1249a, ncp1249b http://onsemi.com 23 frequency foldback the reduction of no ? load standby power associated with the need for improving the efficiency, requires a change in the traditional fixed ? frequency type of operation. this controller implements a switching frequency foldback when the feedback voltage passes below a certain level, v fold_fb , set around 1.9 v. at this point, the oscillator turns into a voltage ? controlled oscillator and reduces its switching frequency. the peak current setpoint is following the feedback pin until its level reaches 1 v. below this value, the peak current freezes to v freeze_fb (250 mv or 31% of the maximum 0.8 v setpoint) and the only way to further reduce the transmitted power is to diminish the operating frequency down to 26 khz. this value is reached at a voltage feedback level of 450 mv typically. below this point, if the output power continues to decrease, the part enters skip cycle for the best noise ? free performance in no ? load conditions. figure 66 depicts the adopted scheme for the part. figure 66. by observing the voltage on the feedback pin, the controller reduces its switching frequency for an improved performance at light load f sw v fold_end v fold_fb 0.80 v v freeze_fb 1.0 v v fold_fb 1.9 v auto ? recovery short ? circuit protection in case of output short ? circuit or if the power supply experiences a severe overloading situation, an internal error flag is raised and starts a countdown timer. if the flag is asserted longer than fault timer duration, the driving pulses are stopped and the v cc capacitor is discharged down to 10 v ( v cc_off threshold) by controller icc consumption. at this point, the controller activates 2 s auto ? recovery timer that starts to count down the time to new restart attempt. the total restart time from fault confirmation is thus given by sum of two times: vcc capacitor discharge time from given vcc level (present at fault confirmation event) to v cc_off level and 2 s internal auto ? recovery timer duration. the v cc capacitor is discharged to vcc _bias level when auto ? recovery timer starts counting. the v cc is maintained at vcc _bias level during this operation to keep timer and other internal circuitry running. the v cc capacitor is fully discharged by x2 discharge switch before controller tries for restart from fault condition. the restart from fault condition is caused when auto ? recovery timer elapses or v cc is forced below 4 v externally. the hv startup current source is activated to charge the vcc capacitor in fast manner to v cc_on level and thus to restart converter operation in case the input line voltage is above v _bo_on threshold. the controller is then checking for the absence of the fault. if the fault is still there, the supply enters another cycle of so ? called hiccup. if the fault has disappeared, the power supply resumes operations. please note that the soft ? start is activated during each of the re ? start sequence. slope compensation the ncp1249 includes an internal ramp compensation signal. this is the buffered oscillator clock delivered during the on time only. its amplitude is around 2.5 v at the maximum authorized duty ? ratio. ramp compensation is a known means used to cure sub harmonic oscillations in ccm ? operated current ? mode converters. these oscillations take place at half the switching frequency and occur only during continuous conduction mode (ccm) with a duty ? ratio greater than 50%. to lower the current loop gain, one usually mixes between 50 and 100% of the inductor downslope with the current ? sense signal. figure 67 depicts how internally the ramp is generated. please note that the ramp signal will be disconnected from the cs pin, during the off ? time.
ncp1249a, ncp1249b http://onsemi.com 24 rsense rcomp 20k 0v 2.5 v cs + ? l.e.b from fb setpoint latch reset on figure 67. inserting a resistor in series with the current sense information brings slope compensation and stabilizes the converter in ccm operation in the ncp1249 controller, the oscillator ramp exhibits a 2.5 v swing reached at a 80% duty ? ratio. if the clock operates at a 65 ? khz frequency, then the available oscillator slope corresponds to: s ramp v ramp d max t sw 2.5 0.8 15 208kv
s or 208mv
s (eq. 9) in our flyback design, let?s assume that our primary inductance l p is 770 h, and the smps delivers 19 v with a n p : n s turns ratio of 1:0.25. the off ? time primary current slope s p is thus given by: s p v out v f n p n s l p ( 19 0.8 ) 4 770 103 ka
s (eq. 10) given a sense resistor of 330 m , the above current ramp turns into a voltage ramp of the following amplitude: s sense s p r sense 103 k 0.33 34 kv
sor34mv
s (eq. 11) if we select 50% of the downslope as the required amount of ramp compensation, then we shall inject a ramp whose slope is 17 mv/ s. our internal compensation being of 208 mv/ s, the divider ratio ( divratio ) between r comp and the internal 20 k resistor is: divratio 17 m 208 m 0.082 (eq. 12) the series compensation resistor value is thus: r comp r ramp divratio 20 k 0.082 1.64 k (eq. 13) a resistor of the above value will then be inserted from the sense resistor to the current sense pin. we recommend adding a small 100 pf capacitor, from the current sense pin to the controller ground for improved noise immunity. please make sure both components are located very close to the controller. latching off the controller the opp pin not only allows a reduction of the peak current set point in relationship to the line voltage, it also offers a means to permanently latch ? off the part. when the part is latched ? off, the vcc pin is internally pulled down to v cc_bias and the part stays in this state until the user un ? plugs the converter from the mains outlet or v cc is forced below 4 v externally. the latch detection is made by observing the opp pin by a comparator featuring a 3 v reference voltage. however, for noise reasons and in particular to avoid the leakage inductance contribution at turn off, a 1 s blanking delay is introduced before the output of the ovp comparator is checked. then, the ovp comparator output is validated only if its high ? state duration lasts a minimum of 600 ns. below this value, the event is ignored. then, a counter ensures that only four successive ovp events have occurred before actually latching the part. there are several possible implementations, depending on the needed precision and the parameters you want to control. the first and easiest solution is the additional resistive divider on top of the opp one. this solution is simple and inexpensive but requires the insertion of a diode to prevent disturbing the opp divider during the on ? time .
ncp1249a, ncp1249b http://onsemi.com 25 4 5 1 opp vlatch 10 8 9 vcc aux. winding opp roppl 1k roppu 421k 11 d2 1n4148 ovp r3 5k c1 100p figure 68. simple resistive divider brings the opp pin above 3 v in case of a v cc voltage runaway above 18 v first, calculate the opp network with the above equations. then, suppose we want to latch off our controller when v out exceeds 25 v. on the auxiliary winding, the plateau reflects the output voltage by the turns ratio between the power and the auxiliary windings. in case of voltage runaway for our 19 v adapter, the plateau will go up to: v aux,ovp 25 0.18 0.25 18 v (eq. 14) since our ovp comparator trips at a 3 v level, across the 1 k selected opp pull ? down resistor, it implies a 3 ma current. from 3 v to go up to 18 v, we need an additional 15 v. under 3 ma and neglecting the series diode forward drop, it requires a series resistor of: r ovp v latch v vop v ovp
r oppl 18 3 3
1k 15 3m 5k (eq. 15) in nominal conditions, the plateau establishes to around 14 v. given the divide ? by ratio 6, the opp pin will swing to 14/6 = 2.3 v during normal conditions, leaving 700 mv for the noise immunity. a 100 pf capacitor can be added to improve it and avoids erratic trips in presence of external surges. do not increase this capacitor too much otherwise the opp signal will be affected by the integrating time constant. a second solution for the ovp detection alone, is to use a zener diode wired as recommended by figure 69. 4 5 1 opp vlatch 10 8 9 vcc aux. winding opp roppl 1k roppu 421k 11 d3 15v d2 1n4148 ovp c1 22pf figure 69. zener diode in series with a diode helps to improve the noise immunity of the system
ncp1249a, ncp1249b http://onsemi.com 26 in this case, to still trip at a 18 v level, we have selected a 15 v zener diode. in nominal conditions, the voltage on the opp pin is almost 0 v during the off time as the zener is fully blocked. this technique clearly improves the noise immunity of the system compared to that obtained from a resistive string as in figure 68. please note the reduction of the capacitor on the opp pin to 10 ? 22 pf. this is because of the potential spike going through the zener parasitic capacitor and the possible auxiliary level shortly exceeding its breakdown voltage during the leakage inductance reset period (hence the internal 1 s blanking delay at turn off). this spike despite its very short time is energetic enough to charge the added capacitor c 1 and given the time constant, could make it discharge slower, potentially disturbing the blanking circuit. when implementing the zener option, it is important to carefully observe the opp pin voltage (short probe connections!) and check that enough margin exists to that respect. internal and external over temperature protection the ncp1249 includes a temperature shutdown protection. when the temperature rises above the high threshold during stable operation ? i.e. start ? up sequence is ended and v cc is between v cc_on and v cc_off levels, the controller immediately stops driver pulses. after the temperature falls back below the lower threshold, the v cc capacitor is fully discharged by x2 discharge switch to restart the controller. the tsd protection can be activated at some other cases (charging v cc capacitor ? start ? up sequence and discharging x2 or v cc capacitors). the tsd protection only interrupts current operating sequence ? i.e. the operation sequence continue after the temperature falls back below the lower threshold. the controller is not reset by tsd activation in these cases. in a lot of designs, the adapter must be protected against thermal runaways, e.g. when the temperature inside the adapter box increases beyond a certain value. figure 70 shows how to implement a simple otp using an external ntc and a series diode. the principle remains the same: make sure the opp network is not bothered by the additional ntc hence the presence of this diode. when the ntc resistor will diminish as the temperature increases, the voltage on the opp pin during the off time will slowly increase and, once it crosses 3 v for 4 consecutive clock cycles, the controller will permanently latch off. opp vlatch vcc aux. winding opp roppl 2.5k ntc d2 1n4148 roppu 841k full latch figure 70. the internal circuitry hooked to pin 1 can be used to implement over temperature protection (otp)
ncp1249a, ncp1249b http://onsemi.com 27 back to our 19 v adapter, we have found that the plateau voltage on the auxiliary diode was 13 v in nominal conditions. we have selected an ntc which offers a 470 k resistor at 25 c and drops to 8.8 k at 110 c. if our auxiliary winding plateau is 14 v and we consider a 0.6 v forward drop for the diode, then the voltage across the ntc in fault mode must be: v ntc 14 3 0.6 10.4 v (eq. 16) based on the 8.8 k ntc resistor at 110 c, the current inside the device must be: i ntc 10.4 8.8 k 1.2 ma (eq. 17) as such, the bottom resistor r oppl , can easily be calculated: r oppl 3 1.2 m 2.5 k (eq. 18) now that the pull ? down opp resistor is known, we can calculate the upper resistor value r oppu to adjust the power limit at the chosen output power level. suppose we need a 200 mv decrease from the 0.8 v set point and the on ? time swing on the auxiliary anode is ? 67.5 v, then we need to drop over r oppu a voltage of: v r oppu 67.5 0.2 67.3 v (eq. 19) the current circulating in the pull down resistor r oppl in this condition will be: i r oppl 200 m 2.5 k 80 a (eq. 20) the r oppu value is therefore easily derived: r oppu 67.3 80 841 k (eq. 21) combining ovp and otp the otp and zener ? based ovp can be combined together as illustrated by figure 71. 4 5 1 opp vlatch 10 8 9 vcc aux. winding opp roppl 2.5k 11 ntc d2 1n4148 roppu 841k d3 15v ovp figure 71. with the ntc back in place, the circuit nicely combines ovp, otp and opp on the same pin in nominal v cc /output conditions, when the zener is not activated, the ntc can drive the opp pin and trigger the adapter in case of a fault. on the contrary, in nominal temperature conditions, if the loop is broken, the voltage runaway will be detected and acknowledged by the controller. in case the opp pin is not used for either opp or ovp, it can simply be grounded. filtering the spikes the auxiliary winding is the seat of spikes that can couple to the opp pin via the parasitic capacitances exhibited by the zener diode and the series diode. to prevent an adverse triggering of the over voltage protection circuitry, it is possible to install a small rc filter before the detection network. typical values are those given in figure 72 and must be selected to provide the adequate filtering function without degrading the stand ? by power by an excessive current circulation.
ncp1249a, ncp1249b http://onsemi.com 28 4 5 1 opp vlatch 10 3 9 vcc aux. winding opp roppl 2.5k 11 ntc 2 d2 1n4148 roppu 841k d3 15v ovp r3 220 c1 330pf additional filter figure 72. a small rc filter avoids the fast rising spikes from reaching the protection pin of the ncp1249 in presence of energetic perturbations superimposed on the input line latching off with the vcc pin the ncp1249 hosts a dedicated comparator on the vcc pin. when the voltage on this pin exceeds 27.5 v typically for more than 20 s, a signal is sent to the internal latch and the controller immediately stops the driving pulses while remaining in a lockout state. the part can be reset when the user disconnects the adapter from the mains. this technique offers a simple and cheaper means to protect the converter against optocoupler failures without using the opp pin and a zener diode. peak power excursions there are applications where the load profile heavily changes from a nominal to a peak value. for instance, it is possible that a 30 w ac ? dc adapter accepts power excursions up to 60 w in certain conditions. inkjet printers typically fall in that category of peak power adapters. however, to avoid growing the transformer size, an existing technique consists in freezing the peak current to a maximum value (0.8/ r sense in our case) but authorizes frequency increase to a certain point. this point is internally fixed at 130 khz. figure 73. the feedback pin modulates the frequency up to 130 khz (short ? circuit, maximum power) or down to 26 khz in frequency foldback
ncp1249a, ncp1249b http://onsemi.com 29 figure 73 shows the voltage evolution from almost 0 v to the open ? loop level, around 4.5 v. at low power levels or in no ? load operation, the feedback voltage stays in the vicinity of 400 mv and ensures skip ? cycle operation. in this mode, the peak current is frozen to 31% of its maximum value and the operating frequency is 26 khz. this freeze lasts as long as v fb stays below 1 v. beyond 1 v, the peak current is authorized to follow v fb through a ratio of 4. when the power demand goes further up, the feedback pin crosses a level of 1.5 v where the switching frequency linearly increases from 26 khz up to 65 khz, a value reached when the feedback voltage exceeds 1.9 v. beyond 1.9 v, the frequency no longer changes. as v fb still increases, the controller is in a fixed ? frequency variable peak current mode control type of operation until the feedback voltage hits 3.2 v. at this point, the maximum current is limited to 0.8 v/ r sense . if v fb further increases, it means the converter undergoes an overload and requires more power from the source. as the peak current excursion is stopped, the only way to deliver more power is to increase the switching frequency. from 3.2 v up to 4.1 v, the frequency linearly increases from 65 khz to 130 khz. beyond 4.1 v, the frequency is fixed to 130 khz. the maximum power delivered by the converter depends whether it operates in discontinuous conduction mode (dcm) or in continuous conduction mode (ccm): p max,dcm 1 2 l p f osc_max i peak,max 2 (eq. 22) p max,ccm 1 2 l p f osc_max i peak,max 2 i valley 2 (eq. 23) where i peak,max is the maximum peak current authorized by the controller and i valley the valley current reached just before a new switching cycle begins. this current is expressed by the following formula: i valley i peak v out v f nl p t off (eq. 24) in dcm, the valley current is equal to 0. two levels of protection once the feedback voltage asks for the maximum peak current, the controller knows that an overload condition has started. an internal timer is operated as soon as the maximum peak is reached. if the feedback voltage continues its rise, it means that the converter output voltage is going down further, close to a short ? circuit situation. when the feedback voltage reaches the open ? loop level (above 4.1 v typically), the original timer duration is divided by 4. of course, if the feedback does not stay that long in the region of concern, the timer is reset when returning to a normal level. figure 74 shows the timer values versus the feedback voltage. figure 74. depending on the feedback level, the timer will take two different values: it will authorize a transient overload, but will reduce a short ? circuit duration
ncp1249a, ncp1249b http://onsemi.com 30 please note that the overload situation (ovl) is detected when the maximum peak current limit is hit. it can be 3.2 v as indicated in the graph in case of no over power protection (opp). if you have programmed an opp level of ? 200 mv for instance, the ovl threshold becomes (0.8 ? 0.2) x 4 = 2.4 v. when the maximum peak current situation is lifted, the converter returns to a normal situation, the timer is reset. the short circuit situation is detected by sensing a feedback voltage beyond 4.1 v. for the sake of the explanation, we have gathered two different events in figure 75 (v ct is voltage on internal capacitor which defines fault timer duration). figure 75. when the feedback voltage exits a fault region before time completion, the timer is reset. on the contrary, if the timer elapses, the part enters an auto ? recovery hiccup or latches off depending on the operated version. in the first case, the feedback is pushed to the maximum upon start ? up. the timer starts with a charging slope of the short ? circuit condition (sc). as soon as regulation occurs, the timer gets reset. an overload occurs shortly after (ovl). the internal timer immediately starts to count when the 3.2 v level is crossed (v fb with no opp). as the overload lasts less than the fault timer elapses, the feedback returns to its regulation level and resets the timer. in the second case, the overload occurs after regulation but the feedback voltage quickly jumps into the short ? circuit area. at this point, the countdown is accelerated as the charging slope changed to a steeper one. the load goes back to an ovl mode and the counter slows down. finally, back to short circuit again and the timer trips the fault circuitry after completion: all pulses are immediately stopped.
ncp1249a, ncp1249b http://onsemi.com 31 package dimensions soic ? 9 nb case 751bp issue a seating plane 1 5 6 10 h x 45 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.10mm total in excess of ?b? at maximum material condition. 4. dimensions d and e do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15mm per side. dimensions d and e are de- termined at datum f. 5. dimensions a and b are to be determ- ined at datum f. 6. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. d e h a1 a dim d min max 4.80 5.00 millimeters e 3.80 4.00 a 1.25 1.75 b 0.31 0.51 e 1.00 bsc a1 0.10 0.25 a3 0.17 0.25 l 0.40 1.27 m 0 8 h 5.80 6.20 c m 0.25 m dimension: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.37 ref l2 0.25 bsc a c 0.20 4 tips top view c 0.20 5 tips a-b d c 0.10 a-b 2x c 0.10 a-b 2x e c 0.10 b 9x b c c 0.10 9x side view end view detail a 6.50 9x 1.18 9x 0.58 1.00 pitch recommended 1 l f seating plane c l2 a3 detail a d on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp1249a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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